# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx8ulp-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ULP Clock Control Module Binding

maintainers:
  - Jacky Bai <ping.bai@nxp.com>

description: |
  On i.MX8ULP, The clock sources generation, distribution and management is
  under the control of several CGCs & PCCs modules. The CGC modules generate
  and distribute clocks on the device. PCC modules control clock selection,
  optional division and clock gating mode for peripherals

properties:
  compatible:
    enum:
      - fsl,imx8ulp-cgc1
      - fsl,imx8ulp-cgc2
      - fsl,imx8ulp-pcc3
      - fsl,imx8ulp-pcc4
      - fsl,imx8ulp-pcc5

  reg:
    maxItems: 1

  clocks:
    description:
      specify the external clocks used by the CGC module, the clocks
      are rosc, sosc, frosc, lposc
    maxItems: 4

  clock-names:
    description:
      specify the external clocks names used by the CGC module. the valid
      clock names should rosc, sosc, frosc, lposc.
    maxItems: 4

  '#clock-cells':
    const: 1
    description:
      The clock consumer should specify the desired clock by having the clock
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8ulp-clock.h
      for the full list of i.MX8ULP clock IDs.

  '#reset-cells':
    const: 1
    description:
      The reset consumer should specify the desired clock by having the reset
      ID in its "resets" phandle cell. See include/dt-bindings/reset/imx8ulp-pcc-reset.h
      for the full list of i.MX8ULP reset IDs. Only PCC3, PCC4 and PCC5 should specify
      this property.

required:
  - compatible
  - reg
  - '#clock-cells'

if:
  properties:
     compatible:
       contains:
         enum:
           - fsl,imx8ulp-pcc3
           - fsl,imx8ulp-pcc4
           - fsl,imx8ulp-pcc5
then:
  required:
    - '#reset-cells'

additionalProperties: false

examples:
  # Clock Control Module node:
  - |
    clock-controller@292c0000 {
        compatible = "fsl,imx8ulp-cgc1";
        reg = <0x292c0000 0x10000>;
        clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
        clock-names = "rosc", "sosc", "frosc", "lposc";
        #clock-cells = <1>;
    };

  - |
    clock-controller@292d0000 {
        compatible = "fsl,imx8ulp-pcc3";
        reg = <0x292d0000 0x10000>;
        #clock-cells = <1>;
        #reset-cells = <1>;
    };
