# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/nxp,imx8ulp-dcnano.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP i.MX8ulp DCNANO display controller

maintainers:
  - Liu Ying <victor.liu@nxp.com>

description: |
  The NXP i.MX8ulp DCNANO display controller is a high-performance graphics
  core that can be used for reading rendered images from the frame buffer.
  In addition to providing hardware cursor patterns, the display controller
  performs format conversions, dithering and gamma corrections.  The display
  controller supports either Display Pixel Interface-2(DPI-2) or Display Bus
  Interface 2.0(DBI-2).

properties:
  compatible:
    const: nxp,imx8ulp-dcnano

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    maxItems: 3

  clock-names:
    items:
      - const: axi
      - const: ahb
      - const: pixel

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  assigned-clocks: true
  assigned-clock-parents: true

  ports:
    $ref: /schemas/graph.yaml#/properties/ports

    properties:
      port@0:
        $ref: /schemas/graph.yaml#/properties/port
        description: The DCNANO DPI-2 output port node.

      port@1:
        $ref: /schemas/graph.yaml#/properties/port
        description: The DCNANO DBI-2 output port node.

    required:
      - port@0
      - port@1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - resets
  - power-domains
  - ports

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/imx8ulp-clock.h>
    #include <dt-bindings/power/imx8ulp-power.h>
    #include <dt-bindings/reset/imx8ulp-pcc-reset.h>
    dcnano: display-controller@2e050000 {
        compatible = "nxp,imx8ulp-dcnano";
        reg = <0x2e050000 0x10000>;
        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>,
                 <&cgc2 IMX8ULP_CLK_LPAV_AHB_DIV>,
                 <&pcc5 IMX8ULP_CLK_DC_NANO>;
        clock-names = "axi", "ahb", "pixel";
        resets = <&pcc5 PCC5_DC_NANO_SWRST>;
        power-domains = <&scmi_devpd IMX8ULP_PD_DCNANO>;
        assigned-clocks = <&pcc5 IMX8ULP_CLK_DC_NANO>;
        assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            dcnano_dpi: port@0 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;

                dcnano_dpi_to_mipi_dsi: endpoint@0 {
                    reg = <0>;
                };

                dcnano_dpi_to_disp: endpoint@1 {
                    reg = <1>;
                };
            };

            dcnano_dbi: port@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;

                dcnano_dbi_to_mipi_dsi: endpoint@0 {
                    reg = <0>;
                };

                dcnano_dbi_to_disp: endpoint@1 {
                    reg = <1>;
                };
            };
        };
    };
