Index of /build/tmp/work/x86_64-nativesdk-tdxsdk-linux/binutils-cross-canadian-aarch64/2.38-r0/git/sim/testsuite/bfin/
../
10272_small.s 17-Feb-2025 10:17 672
10436.s 17-Feb-2025 10:17 332
10622.s 17-Feb-2025 10:17 235
10742.s 17-Feb-2025 10:17 163
10799.s 17-Feb-2025 10:17 708
11080.s 17-Feb-2025 10:17 572
7641.s 17-Feb-2025 10:17 674
ChangeLog-2021 17-Feb-2025 10:17 19658
PN_generator.s 17-Feb-2025 10:17 2077
a0.s 17-Feb-2025 10:17 219
a0shift.S 17-Feb-2025 10:17 3583
a1.s 17-Feb-2025 10:17 470
a10.s 17-Feb-2025 10:17 4386
a11.S 17-Feb-2025 10:17 6439
a12.s 17-Feb-2025 10:17 580
a2.s 17-Feb-2025 10:17 3313
a20.S 17-Feb-2025 10:17 925
a21.s 17-Feb-2025 10:17 1750
a22.s 17-Feb-2025 10:17 1409
a23.s 17-Feb-2025 10:17 1456
a24.s 17-Feb-2025 10:17 156
a25.s 17-Feb-2025 10:17 350
a26.s 17-Feb-2025 10:17 962
a3.s 17-Feb-2025 10:17 9974
a30.s 17-Feb-2025 10:17 877
a4.s 17-Feb-2025 10:17 314
a5.s 17-Feb-2025 10:17 3100
a6.s 17-Feb-2025 10:17 2983
a7.s 17-Feb-2025 10:17 2632
a8.s 17-Feb-2025 10:17 626
a9.s 17-Feb-2025 10:17 5570
abs-2.S 17-Feb-2025 10:17 800
abs-3.S 17-Feb-2025 10:17 784
abs-4.S 17-Feb-2025 10:17 802
abs.S 17-Feb-2025 10:17 800
abs_acc.s 17-Feb-2025 10:17 2751
acc-rot.s 17-Feb-2025 10:17 5247
acp5_19.s 17-Feb-2025 10:17 143
acp5_4.s 17-Feb-2025 10:17 647
add_imm7.s 17-Feb-2025 10:17 415
add_shift.S 17-Feb-2025 10:17 796
add_sub_acc.s 17-Feb-2025 10:17 1335
addsub_flags.S 17-Feb-2025 10:17 1605
algnbug1.s 17-Feb-2025 10:17 559
algnbug2.s 17-Feb-2025 10:17 1181
allinsn.exp 17-Feb-2025 10:17 554
argc.c 17-Feb-2025 10:17 484
ashift.s 17-Feb-2025 10:17 10985
ashift_flags.s 17-Feb-2025 10:17 1180
ashift_left.s 17-Feb-2025 10:17 252
b0.S 17-Feb-2025 10:17 854
b1.s 17-Feb-2025 10:17 117
b2.S 17-Feb-2025 10:17 416
brcc.s 17-Feb-2025 10:17 1725
brevadd.s 17-Feb-2025 10:17 229
byteop16m.s 17-Feb-2025 10:17 2905
byteop16p.s 17-Feb-2025 10:17 2889
byteop1p.s 17-Feb-2025 10:17 2862
byteop2p.s 17-Feb-2025 10:17 1856
byteop3p.s 17-Feb-2025 10:17 5233
byteunpack.s 17-Feb-2025 10:17 1203
c_alu2op_arith_r_sft.s 17-Feb-2025 10:17 4138
c_alu2op_conv_b.s 17-Feb-2025 10:17 4130
c_alu2op_conv_h.s 17-Feb-2025 10:17 4130
c_alu2op_conv_mix.s 17-Feb-2025 10:17 3583
c_alu2op_conv_neg.s 17-Feb-2025 10:17 3881
c_alu2op_conv_toggle.s 17-Feb-2025 10:17 3885
c_alu2op_conv_xb.s 17-Feb-2025 10:17 4133
c_alu2op_conv_xh.s 17-Feb-2025 10:17 4134
c_alu2op_divq.s 17-Feb-2025 10:17 4425
c_alu2op_divs.s 17-Feb-2025 10:17 4425
c_alu2op_log_l_sft.s 17-Feb-2025 10:17 4171
c_alu2op_log_r_sft.s 17-Feb-2025 10:17 4072
c_alu2op_shadd_1.s 17-Feb-2025 10:17 4640
c_alu2op_shadd_2.s 17-Feb-2025 10:17 4640
c_br_preg_killed_ac.s 17-Feb-2025 10:17 1667
c_br_preg_killed_ex1.s 17-Feb-2025 10:17 1598
c_br_preg_stall_ac.s 17-Feb-2025 10:17 1426
c_br_preg_stall_ex1.s 17-Feb-2025 10:17 1280
c_brcc_bp1.s 17-Feb-2025 10:17 1052
c_brcc_bp2.s 17-Feb-2025 10:17 1057
c_brcc_bp3.s 17-Feb-2025 10:17 1064
c_brcc_bp4.s 17-Feb-2025 10:17 1068
c_brcc_brf_bp.s 17-Feb-2025 10:17 1066
c_brcc_brf_brt_bp.s 17-Feb-2025 10:17 1096
c_brcc_brf_brt_nbp.s 17-Feb-2025 10:17 1075
c_brcc_brf_fbkwd.s 17-Feb-2025 10:17 705
c_brcc_brf_nbp.s 17-Feb-2025 10:17 1050
c_brcc_brt_bp.s 17-Feb-2025 10:17 987
c_brcc_brt_nbp.s 17-Feb-2025 10:17 967
c_brcc_kills_dhits.s 17-Feb-2025 10:17 2555
c_brcc_kills_dmiss.s 17-Feb-2025 10:17 2562
c_cactrl_iflush_pr.s 17-Feb-2025 10:17 1898
c_cactrl_iflush_pr_pp.s 17-Feb-2025 10:17 1885
c_calla_ljump.s 17-Feb-2025 10:17 511
c_calla_subr.s 17-Feb-2025 10:17 475
c_cc2dreg.s 17-Feb-2025 10:17 701
c_cc2stat_cc_ac.S 17-Feb-2025 10:17 4305
c_cc2stat_cc_an.s 17-Feb-2025 10:17 4017
c_cc2stat_cc_aq.s 17-Feb-2025 10:17 4081
c_cc2stat_cc_av0.S 17-Feb-2025 10:17 4328
c_cc2stat_cc_av1.S 17-Feb-2025 10:17 4303
c_cc2stat_cc_az.s 17-Feb-2025 10:17 4017
c_cc_flag_ccmv_depend.S 17-Feb-2025 10:17 1626
c_cc_flagdreg_mvbrsft.s 17-Feb-2025 10:17 1709
c_cc_flagdreg_mvbrsft_s1.s 17-Feb-2025 10:17 2422
c_cc_flagdreg_mvbrsft_sn.s 17-Feb-2025 10:17 2888
c_cc_regmvlogi_mvbrsft.s 17-Feb-2025 10:17 1803
c_cc_regmvlogi_mvbrsft_s1.s 17-Feb-2025 10:17 2330
c_cc_regmvlogi_mvbrsft_sn.S 17-Feb-2025 10:17 3142
c_ccflag_a0a1.S 17-Feb-2025 10:17 2651
c_ccflag_dr_dr.s 17-Feb-2025 10:17 5401
c_ccflag_dr_dr_uu.s 17-Feb-2025 10:17 5610
c_ccflag_dr_imm3.s 17-Feb-2025 10:17 3795
c_ccflag_dr_imm3_uu.s 17-Feb-2025 10:17 3836
c_ccflag_pr_imm3.s 17-Feb-2025 10:17 8819
c_ccflag_pr_imm3_uu.s 17-Feb-2025 10:17 4076
c_ccflag_pr_pr.s 17-Feb-2025 10:17 4804
c_ccflag_pr_pr_uu.s 17-Feb-2025 10:17 4150
c_ccmv_cc_dr_dr.s 17-Feb-2025 10:17 2256
c_ccmv_cc_dr_pr.s 17-Feb-2025 10:17 1217
c_ccmv_cc_pr_pr.s 17-Feb-2025 10:17 2175
c_ccmv_ncc_dr_dr.s 17-Feb-2025 10:17 2290
c_ccmv_ncc_dr_pr.s 17-Feb-2025 10:17 1209
c_ccmv_ncc_pr_pr.s 17-Feb-2025 10:17 2210
c_comp3op_dr_and_dr.s 17-Feb-2025 10:17 7992
c_comp3op_dr_minus_dr.s 17-Feb-2025 10:17 7996
c_comp3op_dr_mix.s 17-Feb-2025 10:17 4520
c_comp3op_dr_or_dr.s 17-Feb-2025 10:17 7990
c_comp3op_dr_plus_dr.s 17-Feb-2025 10:17 7994
c_comp3op_dr_xor_dr.s 17-Feb-2025 10:17 7994
c_comp3op_pr_plus_pr_sh1.s 17-Feb-2025 10:17 7005
c_comp3op_pr_plus_pr_sh2.s 17-Feb-2025 10:17 7005
c_compi2opd_dr_add_i7_n.s 17-Feb-2025 10:17 2790
c_compi2opd_dr_add_i7_p.s 17-Feb-2025 10:17 2438
c_compi2opd_dr_eq_i7_n.s 17-Feb-2025 10:17 2204
c_compi2opd_dr_eq_i7_p.s 17-Feb-2025 10:17 1849
c_compi2opd_flags.S 17-Feb-2025 10:17 14926
c_compi2opd_flags_2.S 17-Feb-2025 10:17 14915
c_compi2opp_pr_add_i7_n.s 17-Feb-2025 10:17 2735
c_compi2opp_pr_add_i7_p.s 17-Feb-2025 10:17 2063
c_compi2opp_pr_eq_i7_n.s 17-Feb-2025 10:17 2415
c_compi2opp_pr_eq_i7_p.s 17-Feb-2025 10:17 1850
c_dagmodik_lnz_imgebl.s 17-Feb-2025 10:17 4311
c_dagmodik_lnz_imltbl.s 17-Feb-2025 10:17 4307
c_dagmodik_lz_inc_dec.s 17-Feb-2025 10:17 2078
c_dagmodim_lnz_imgebl.s 17-Feb-2025 10:17 1693
c_dagmodim_lnz_imltbl.s 17-Feb-2025 10:17 1691
c_dagmodim_lz_inc_dec.s 17-Feb-2025 10:17 1531
c_dsp32alu_a0_pm_a1.s 17-Feb-2025 10:17 559
c_dsp32alu_a0a1s.s 17-Feb-2025 10:17 1313
c_dsp32alu_a_abs_a.s 17-Feb-2025 10:17 513
c_dsp32alu_a_neg_a.s 17-Feb-2025 10:17 505
c_dsp32alu_aa_absabs.s 17-Feb-2025 10:17 576
c_dsp32alu_aa_negneg.s 17-Feb-2025 10:17 568
c_dsp32alu_abs.s 17-Feb-2025 10:17 1135
c_dsp32alu_absabs.s 17-Feb-2025 10:17 1211
c_dsp32alu_alhwx.s 17-Feb-2025 10:17 2414
c_dsp32alu_awx.s 17-Feb-2025 10:17 958
c_dsp32alu_byteop1ew.s 17-Feb-2025 10:17 3633
c_dsp32alu_byteop2.s 17-Feb-2025 10:17 1967
c_dsp32alu_byteop3.s 17-Feb-2025 10:17 1919
c_dsp32alu_bytepack.s 17-Feb-2025 10:17 1701
c_dsp32alu_byteunpack.s 17-Feb-2025 10:17 2825
c_dsp32alu_disalnexcpt.s 17-Feb-2025 10:17 4523
c_dsp32alu_max.s 17-Feb-2025 10:17 5702
c_dsp32alu_maxmax.s 17-Feb-2025 10:17 6034
c_dsp32alu_min.s 17-Feb-2025 10:17 5702
c_dsp32alu_minmin.s 17-Feb-2025 10:17 6034
c_dsp32alu_mix.s 17-Feb-2025 10:17 4000
c_dsp32alu_r_lh_a0pa1.s 17-Feb-2025 10:17 1458
c_dsp32alu_r_negneg.s 17-Feb-2025 10:17 1671
c_dsp32alu_rh_m.s 17-Feb-2025 10:17 5914
c_dsp32alu_rh_p.s 17-Feb-2025 10:17 5914
c_dsp32alu_rh_rnd12_m.s 17-Feb-2025 10:17 6112
c_dsp32alu_rh_rnd12_p.s 17-Feb-2025 10:17 6136
c_dsp32alu_rh_rnd20_m.s 17-Feb-2025 10:17 5857
c_dsp32alu_rh_rnd20_p.s 17-Feb-2025 10:17 5857
c_dsp32alu_rl_m.s 17-Feb-2025 10:17 5914
c_dsp32alu_rl_p.s 17-Feb-2025 10:17 5914
c_dsp32alu_rl_rnd12_m.s 17-Feb-2025 10:17 6135
c_dsp32alu_rl_rnd12_p.s 17-Feb-2025 10:17 6136
c_dsp32alu_rl_rnd20_m.s 17-Feb-2025 10:17 5957
c_dsp32alu_rl_rnd20_p.s 17-Feb-2025 10:17 5857
c_dsp32alu_rlh_rnd.s 17-Feb-2025 10:17 1239
c_dsp32alu_rm.s 17-Feb-2025 10:17 5417
c_dsp32alu_rmm.s 17-Feb-2025 10:17 5429
c_dsp32alu_rmp.s 17-Feb-2025 10:17 5429
c_dsp32alu_rp.s 17-Feb-2025 10:17 5417
c_dsp32alu_rpm.s 17-Feb-2025 10:17 5429
c_dsp32alu_rpp.s 17-Feb-2025 10:17 5431
c_dsp32alu_rr_lph_a1a0.s 17-Feb-2025 10:17 654
c_dsp32alu_rrpm.s 17-Feb-2025 10:17 6562
c_dsp32alu_rrpm_aa.s 17-Feb-2025 10:17 1513
c_dsp32alu_rrpmmp.s 17-Feb-2025 10:17 6686
c_dsp32alu_rrpmmp_sft.s 17-Feb-2025 10:17 7367
c_dsp32alu_rrpmmp_sft_x.s 17-Feb-2025 10:17 7770
c_dsp32alu_rrppmm.s 17-Feb-2025 10:17 6606
c_dsp32alu_rrppmm_sft.s 17-Feb-2025 10:17 7286
c_dsp32alu_rrppmm_sft_x.s 17-Feb-2025 10:17 7692
c_dsp32alu_saa.s 17-Feb-2025 10:17 1347
c_dsp32alu_sat_aa.S 17-Feb-2025 10:17 726
c_dsp32alu_search.s 17-Feb-2025 10:17 1669
c_dsp32alu_sgn.s 17-Feb-2025 10:17 1056
c_dsp32mac_a1a0.s 17-Feb-2025 10:17 5188
c_dsp32mac_a1a0_iuw32.s 17-Feb-2025 10:17 21914
c_dsp32mac_a1a0_m.s 17-Feb-2025 10:17 6857
c_dsp32mac_dr_a0.s 17-Feb-2025 10:17 2857
c_dsp32mac_dr_a0_i.s 17-Feb-2025 10:17 2839
c_dsp32mac_dr_a0_ih.s 17-Feb-2025 10:17 2875
c_dsp32mac_dr_a0_is.s 17-Feb-2025 10:17 2901
c_dsp32mac_dr_a0_iu.s 17-Feb-2025 10:17 2761
c_dsp32mac_dr_a0_m.s 17-Feb-2025 10:17 2922
c_dsp32mac_dr_a0_s.s 17-Feb-2025 10:17 2911
c_dsp32mac_dr_a0_t.s 17-Feb-2025 10:17 2822
c_dsp32mac_dr_a0_tu.s 17-Feb-2025 10:17 2876
c_dsp32mac_dr_a0_u.s 17-Feb-2025 10:17 2860
c_dsp32mac_dr_a1.s 17-Feb-2025 10:17 5142
c_dsp32mac_dr_a1_i.s 17-Feb-2025 10:17 6719
c_dsp32mac_dr_a1_ih.s 17-Feb-2025 10:17 3520
c_dsp32mac_dr_a1_is.s 17-Feb-2025 10:17 3544
c_dsp32mac_dr_a1_iu.s 17-Feb-2025 10:17 3498
c_dsp32mac_dr_a1_m.s 17-Feb-2025 10:17 4815
c_dsp32mac_dr_a1_s.s 17-Feb-2025 10:17 3576
c_dsp32mac_dr_a1_t.s 17-Feb-2025 10:17 6681
c_dsp32mac_dr_a1_tu.s 17-Feb-2025 10:17 3526
c_dsp32mac_dr_a1_u.s 17-Feb-2025 10:17 4138
c_dsp32mac_dr_a1a0.s 17-Feb-2025 10:17 3814
c_dsp32mac_dr_a1a0_iutsh.s 17-Feb-2025 10:17 3937
c_dsp32mac_dr_a1a0_m.s 17-Feb-2025 10:17 3885
c_dsp32mac_mix.s 17-Feb-2025 10:17 3068
c_dsp32mac_pair_a0.s 17-Feb-2025 10:17 3226
c_dsp32mac_pair_a0_i.s 17-Feb-2025 10:17 6250
c_dsp32mac_pair_a0_is.s 17-Feb-2025 10:17 6280
c_dsp32mac_pair_a0_m.s 17-Feb-2025 10:17 3122
c_dsp32mac_pair_a0_s.s 17-Feb-2025 10:17 6303
c_dsp32mac_pair_a0_u.s 17-Feb-2025 10:17 6210
c_dsp32mac_pair_a1.s 17-Feb-2025 10:17 3192
c_dsp32mac_pair_a1_i.s 17-Feb-2025 10:17 6096
c_dsp32mac_pair_a1_is.s 17-Feb-2025 10:17 6164
c_dsp32mac_pair_a1_m.s 17-Feb-2025 10:17 3011
c_dsp32mac_pair_a1_s.s 17-Feb-2025 10:17 6193
c_dsp32mac_pair_a1_u.s 17-Feb-2025 10:17 6093
c_dsp32mac_pair_a1a0.s 17-Feb-2025 10:17 3821
c_dsp32mac_pair_a1a0_i.s 17-Feb-2025 10:17 7450
c_dsp32mac_pair_a1a0_is.s 17-Feb-2025 10:17 7512
c_dsp32mac_pair_a1a0_m.s 17-Feb-2025 10:17 3798
c_dsp32mac_pair_a1a0_s.s 17-Feb-2025 10:17 7686
c_dsp32mac_pair_a1a0_u.s 17-Feb-2025 10:17 7454
c_dsp32mac_pair_mix.s 17-Feb-2025 10:17 1700
c_dsp32mult_dr.s 17-Feb-2025 10:17 5800
c_dsp32mult_dr_i.s 17-Feb-2025 10:17 6094
c_dsp32mult_dr_ih.s 17-Feb-2025 10:17 6097
c_dsp32mult_dr_is.s 17-Feb-2025 10:17 6225
c_dsp32mult_dr_iu.s 17-Feb-2025 10:17 6097
c_dsp32mult_dr_m.s 17-Feb-2025 10:17 4503
c_dsp32mult_dr_m_i.s 17-Feb-2025 10:17 4844
c_dsp32mult_dr_m_iutsh.s 17-Feb-2025 10:17 4916
c_dsp32mult_dr_m_s.s 17-Feb-2025 10:17 5036
c_dsp32mult_dr_m_t.s 17-Feb-2025 10:17 4780
c_dsp32mult_dr_m_u.s 17-Feb-2025 10:17 4844
c_dsp32mult_dr_mix.s 17-Feb-2025 10:17 5477
c_dsp32mult_dr_s.s 17-Feb-2025 10:17 6286
c_dsp32mult_dr_t.s 17-Feb-2025 10:17 6030
c_dsp32mult_dr_tu.s 17-Feb-2025 10:17 6161
c_dsp32mult_dr_u.s 17-Feb-2025 10:17 6094
c_dsp32mult_pair.s 17-Feb-2025 10:17 4358
c_dsp32mult_pair_i.s 17-Feb-2025 10:17 4524
c_dsp32mult_pair_is.s 17-Feb-2025 10:17 4591
c_dsp32mult_pair_m.s 17-Feb-2025 10:17 3767
c_dsp32mult_pair_m_i.s 17-Feb-2025 10:17 3933
c_dsp32mult_pair_m_is.s 17-Feb-2025 10:17 4000
c_dsp32mult_pair_m_s.s 17-Feb-2025 10:17 4029
c_dsp32mult_pair_m_u.s 17-Feb-2025 10:17 3933
c_dsp32mult_pair_s.s 17-Feb-2025 10:17 4621
c_dsp32mult_pair_u.s 17-Feb-2025 10:17 4524
c_dsp32shift_a0alr.s 17-Feb-2025 10:17 4342
c_dsp32shift_af.s 17-Feb-2025 10:17 4341
c_dsp32shift_af_s.s 17-Feb-2025 10:17 4507
c_dsp32shift_ahalf_ln.s 17-Feb-2025 10:17 10070
c_dsp32shift_ahalf_ln_s.s 17-Feb-2025 10:17 10594
c_dsp32shift_ahalf_lp.s 17-Feb-2025 10:17 10050
c_dsp32shift_ahalf_lp_s.s 17-Feb-2025 10:17 10526
c_dsp32shift_ahalf_rn.s 17-Feb-2025 10:17 9932
c_dsp32shift_ahalf_rn_s.s 17-Feb-2025 10:17 10386
c_dsp32shift_ahalf_rp.s 17-Feb-2025 10:17 9932
c_dsp32shift_ahalf_rp_s.s 17-Feb-2025 10:17 10384
c_dsp32shift_ahh.s 17-Feb-2025 10:17 10098
c_dsp32shift_ahh_s.s 17-Feb-2025 10:17 10611
c_dsp32shift_align16.s 17-Feb-2025 10:17 4845
c_dsp32shift_align24.s 17-Feb-2025 10:17 4845
c_dsp32shift_align8.s 17-Feb-2025 10:17 4778
c_dsp32shift_amix.s 17-Feb-2025 10:17 3646
c_dsp32shift_bitmux.s 17-Feb-2025 10:17 11276
c_dsp32shift_bxor.s 17-Feb-2025 10:17 3002
c_dsp32shift_expadj_h.s 17-Feb-2025 10:17 5109
c_dsp32shift_expadj_l.s 17-Feb-2025 10:17 5107
c_dsp32shift_expadj_r.s 17-Feb-2025 10:17 4974
c_dsp32shift_expexp_r.s 17-Feb-2025 10:17 5243
c_dsp32shift_fdepx.s 17-Feb-2025 10:17 4760
c_dsp32shift_fextx.s 17-Feb-2025 10:17 5096
c_dsp32shift_lf.s 17-Feb-2025 10:17 9304
c_dsp32shift_lhalf_ln.s 17-Feb-2025 10:17 10070
c_dsp32shift_lhalf_lp.s 17-Feb-2025 10:17 10027
c_dsp32shift_lhalf_rn.s 17-Feb-2025 10:17 9934
c_dsp32shift_lhalf_rp.s 17-Feb-2025 10:17 9932
c_dsp32shift_lhh.s 17-Feb-2025 10:17 7095
c_dsp32shift_lmix.s 17-Feb-2025 10:17 3363
c_dsp32shift_ones.s 17-Feb-2025 10:17 4200
c_dsp32shift_pack.s 17-Feb-2025 10:17 9517
c_dsp32shift_rot.s 17-Feb-2025 10:17 9511
c_dsp32shift_rot_mix.s 17-Feb-2025 10:17 9699
c_dsp32shift_signbits_r.s 17-Feb-2025 10:17 4478
c_dsp32shift_signbits_rh.s 17-Feb-2025 10:17 4611
c_dsp32shift_signbits_rl.s 17-Feb-2025 10:17 4586
c_dsp32shift_vmax.s 17-Feb-2025 10:17 2571
c_dsp32shift_vmaxvmax.s 17-Feb-2025 10:17 2682
c_dsp32shiftim_a0alr.s 17-Feb-2025 10:17 4211
c_dsp32shiftim_af.s 17-Feb-2025 10:17 1166
c_dsp32shiftim_af_s.s 17-Feb-2025 10:17 1212
c_dsp32shiftim_ahalf_ln.s 17-Feb-2025 10:17 8575
c_dsp32shiftim_ahalf_ln_s.s 17-Feb-2025 10:17 9103
c_dsp32shiftim_ahalf_lp.s 17-Feb-2025 10:17 8772
c_dsp32shiftim_ahalf_lp_s.s 17-Feb-2025 10:17 9178
c_dsp32shiftim_ahalf_rn.s 17-Feb-2025 10:17 8703
c_dsp32shiftim_ahalf_rn_s.s 17-Feb-2025 10:17 8707
c_dsp32shiftim_ahalf_rp.s 17-Feb-2025 10:17 8846
c_dsp32shiftim_ahalf_rp_s.s 17-Feb-2025 10:17 8862
c_dsp32shiftim_ahh.s 17-Feb-2025 10:17 1240
c_dsp32shiftim_ahh_s.s 17-Feb-2025 10:17 1310
c_dsp32shiftim_amix.s 17-Feb-2025 10:17 3385
c_dsp32shiftim_lf.s 17-Feb-2025 10:17 1158
c_dsp32shiftim_lhalf_ln.s 17-Feb-2025 10:17 8348
c_dsp32shiftim_lhalf_lp.s 17-Feb-2025 10:17 8752
c_dsp32shiftim_lhalf_rn.s 17-Feb-2025 10:17 8717
c_dsp32shiftim_lhalf_rp.s 17-Feb-2025 10:17 8629
c_dsp32shiftim_lhh.s 17-Feb-2025 10:17 1233
c_dsp32shiftim_lmix.s 17-Feb-2025 10:17 3020
c_dsp32shiftim_rot.s 17-Feb-2025 10:17 1303
c_dspldst_ld_dr_i.s 17-Feb-2025 10:17 2738
c_dspldst_ld_dr_ipp.s 17-Feb-2025 10:17 6197
c_dspldst_ld_dr_ippm.s 17-Feb-2025 10:17 5691
c_dspldst_ld_drhi_i.s 17-Feb-2025 10:17 2946
c_dspldst_ld_drhi_ipp.s 17-Feb-2025 10:17 6609
c_dspldst_ld_drlo_i.s 17-Feb-2025 10:17 2927
c_dspldst_ld_drlo_ipp.s 17-Feb-2025 10:17 6520
c_dspldst_st_dr_i.s 17-Feb-2025 10:17 3104
c_dspldst_st_dr_ipp.s 17-Feb-2025 10:17 5619
c_dspldst_st_dr_ippm.s 17-Feb-2025 10:17 4737
c_dspldst_st_drhi_i.s 17-Feb-2025 10:17 2770
c_dspldst_st_drhi_ipp.s 17-Feb-2025 10:17 6264
c_dspldst_st_drlo_i.s 17-Feb-2025 10:17 2772
c_dspldst_st_drlo_ipp.s 17-Feb-2025 10:17 6260
c_except_illopcode.S 17-Feb-2025 10:17 1831
c_except_sys_sstep.S 17-Feb-2025 10:17 4735
c_except_user_mode.S 17-Feb-2025 10:17 6542
c_interr_disable.S 17-Feb-2025 10:17 6378
c_interr_disable_enable.S 17-Feb-2025 10:17 7342
c_interr_excpt.S 17-Feb-2025 10:17 5517
c_interr_loopsetup_stld.S 17-Feb-2025 10:17 4334
c_interr_nested.S 17-Feb-2025 10:17 5532
c_interr_nmi.S 17-Feb-2025 10:17 6095
c_interr_pending.S 17-Feb-2025 10:17 6415
c_interr_pending_2.S 17-Feb-2025 10:17 5190
c_interr_timer.S 17-Feb-2025 10:17 8283
c_interr_timer_reload.S 17-Feb-2025 10:17 5875
c_interr_timer_tcount.S 17-Feb-2025 10:17 4864
c_interr_timer_tscale.S 17-Feb-2025 10:17 6542
c_ldimmhalf_dreg.s 17-Feb-2025 10:17 1107
c_ldimmhalf_drhi.s 17-Feb-2025 10:17 1452
c_ldimmhalf_drlo.s 17-Feb-2025 10:17 1530
c_ldimmhalf_h_dr.s 17-Feb-2025 10:17 1470
c_ldimmhalf_h_ibml.s 17-Feb-2025 10:17 2744
c_ldimmhalf_h_pr.s 17-Feb-2025 10:17 1441
c_ldimmhalf_l_dr.s 17-Feb-2025 10:17 1470
c_ldimmhalf_l_ibml.s 17-Feb-2025 10:17 2744
c_ldimmhalf_l_pr.s 17-Feb-2025 10:17 1469
c_ldimmhalf_lz_dr.s 17-Feb-2025 10:17 1536
c_ldimmhalf_lz_ibml.s 17-Feb-2025 10:17 2624
c_ldimmhalf_lz_pr.s 17-Feb-2025 10:17 1464
c_ldimmhalf_lzhi_dr.s 17-Feb-2025 10:17 2025
c_ldimmhalf_lzhi_ibml.s 17-Feb-2025 10:17 3350
c_ldimmhalf_lzhi_pr.s 17-Feb-2025 10:17 1952
c_ldimmhalf_pibml.s 17-Feb-2025 10:17 3816
c_ldst_ld_d_p.s 17-Feb-2025 10:17 6193
c_ldst_ld_d_p_b.s 17-Feb-2025 10:17 5922
c_ldst_ld_d_p_h.s 17-Feb-2025 10:17 5916
c_ldst_ld_d_p_mm.s 17-Feb-2025 10:17 7277
c_ldst_ld_d_p_mm_b.s 17-Feb-2025 10:17 6139
c_ldst_ld_d_p_mm_h.s 17-Feb-2025 10:17 5591
c_ldst_ld_d_p_mm_xb.s 17-Feb-2025 10:17 5801
c_ldst_ld_d_p_mm_xh.s 17-Feb-2025 10:17 6180
c_ldst_ld_d_p_pp.s 17-Feb-2025 10:17 6307
c_ldst_ld_d_p_pp_b.s 17-Feb-2025 10:17 5467
c_ldst_ld_d_p_pp_h.s 17-Feb-2025 10:17 5912
c_ldst_ld_d_p_pp_xb.s 17-Feb-2025 10:17 6169
c_ldst_ld_d_p_pp_xh.s 17-Feb-2025 10:17 5622
c_ldst_ld_d_p_ppmm_hbx.s 17-Feb-2025 10:17 13148
c_ldst_ld_d_p_xb.s 17-Feb-2025 10:17 5459
c_ldst_ld_d_p_xh.s 17-Feb-2025 10:17 5915
c_ldst_ld_p_p.s 17-Feb-2025 10:17 5300
c_ldst_ld_p_p_mm.s 17-Feb-2025 10:17 7027
c_ldst_ld_p_p_pp.s 17-Feb-2025 10:17 5457
c_ldst_st_p_d.s 17-Feb-2025 10:17 5343
c_ldst_st_p_d_b.s 17-Feb-2025 10:17 5448
c_ldst_st_p_d_h.s 17-Feb-2025 10:17 5034
c_ldst_st_p_d_mm.s 17-Feb-2025 10:17 10550
c_ldst_st_p_d_mm_b.s 17-Feb-2025 10:17 8410
c_ldst_st_p_d_mm_h.s 17-Feb-2025 10:17 9629
c_ldst_st_p_d_pp.s 17-Feb-2025 10:17 14295
c_ldst_st_p_d_pp_b.s 17-Feb-2025 10:17 7545
c_ldst_st_p_d_pp_h.s 17-Feb-2025 10:17 7579
c_ldst_st_p_p.s 17-Feb-2025 10:17 2019
c_ldst_st_p_p_mm.s 17-Feb-2025 10:17 6993
c_ldst_st_p_p_pp.s 17-Feb-2025 10:17 6402
c_ldstidxl_ld_dr_b.s 17-Feb-2025 10:17 9660
c_ldstidxl_ld_dr_h.s 17-Feb-2025 10:17 10643
c_ldstidxl_ld_dr_xb.s 17-Feb-2025 10:17 10645
c_ldstidxl_ld_dr_xh.s 17-Feb-2025 10:17 10646
c_ldstidxl_ld_dreg.s 17-Feb-2025 10:17 9418
c_ldstidxl_ld_preg.s 17-Feb-2025 10:17 11608
c_ldstidxl_st_dr_b.s 17-Feb-2025 10:17 11066
c_ldstidxl_st_dr_h.s 17-Feb-2025 10:17 11001
c_ldstidxl_st_dreg.s 17-Feb-2025 10:17 13554
c_ldstidxl_st_preg.s 17-Feb-2025 10:17 12527
c_ldstii_ld_dr_h.s 17-Feb-2025 10:17 9484
c_ldstii_ld_dr_xh.s 17-Feb-2025 10:17 9487
c_ldstii_ld_dreg.s 17-Feb-2025 10:17 9187
c_ldstii_ld_preg.s 17-Feb-2025 10:17 9721
c_ldstii_st_dr_h.s 17-Feb-2025 10:17 10521
c_ldstii_st_dreg.s 17-Feb-2025 10:17 10840
c_ldstii_st_preg.s 17-Feb-2025 10:17 10005
c_ldstiifp_ld_dreg.s 17-Feb-2025 10:17 9029
c_ldstiifp_ld_preg.s 17-Feb-2025 10:17 8708
c_ldstiifp_st_dreg.s 17-Feb-2025 10:17 11033
c_ldstiifp_st_preg.s 17-Feb-2025 10:17 10475
c_ldstpmod_ld_dr_hi.s 17-Feb-2025 10:17 7160
c_ldstpmod_ld_dr_lo.s 17-Feb-2025 10:17 7160
c_ldstpmod_ld_dreg.s 17-Feb-2025 10:17 7970
c_ldstpmod_ld_h_xh.s 17-Feb-2025 10:17 8302
c_ldstpmod_ld_lohi.s 17-Feb-2025 10:17 8188
c_ldstpmod_st_dr_hi.s 17-Feb-2025 10:17 7129
c_ldstpmod_st_dr_lo.s 17-Feb-2025 10:17 7130
c_ldstpmod_st_dreg.s 17-Feb-2025 10:17 11453
c_ldstpmod_st_lohi.s 17-Feb-2025 10:17 11838
c_linkage.s 17-Feb-2025 10:17 974
c_logi2op_alshft_mix.s 17-Feb-2025 10:17 3546
c_logi2op_arith_shft.s 17-Feb-2025 10:17 5502
c_logi2op_bitclr.s 17-Feb-2025 10:17 2492
c_logi2op_bitset.s 17-Feb-2025 10:17 2474
c_logi2op_bittgl.s 17-Feb-2025 10:17 4653
c_logi2op_bittst.s 17-Feb-2025 10:17 14760
c_logi2op_log_l_shft.s 17-Feb-2025 10:17 4199
c_logi2op_log_l_shft_astat.S 17-Feb-2025 10:17 1071
c_logi2op_log_r_shft.s 17-Feb-2025 10:17 5431
c_logi2op_log_r_shft_astat.S 17-Feb-2025 10:17 1081
c_logi2op_nbittst.s 17-Feb-2025 10:17 14881
c_loopsetup_nested.s 17-Feb-2025 10:17 2920
c_loopsetup_nested_bot.s 17-Feb-2025 10:17 2891
c_loopsetup_nested_prelc.s 17-Feb-2025 10:17 2963
c_loopsetup_nested_top.s 17-Feb-2025 10:17 2885
c_loopsetup_overlap.s 17-Feb-2025 10:17 2930
c_loopsetup_preg_div2_lc0.s 17-Feb-2025 10:17 1701
c_loopsetup_preg_div2_lc1.s 17-Feb-2025 10:17 1711
c_loopsetup_preg_lc0.s 17-Feb-2025 10:17 1637
c_loopsetup_preg_lc1.s 17-Feb-2025 10:17 1661
c_loopsetup_preg_stld.s 17-Feb-2025 10:17 3298
c_loopsetup_prelc.s 17-Feb-2025 10:17 2286
c_loopsetup_topbotcntr.s 17-Feb-2025 10:17 1668
c_mmr_interr_ctl.s 17-Feb-2025 10:17 7791
c_mmr_loop.S 17-Feb-2025 10:17 8465
c_mmr_loop_user_except.S 17-Feb-2025 10:17 6642
c_mmr_ppop_illegal_adr.S 17-Feb-2025 10:17 6086
c_mmr_ppopm_illegal_adr.S 17-Feb-2025 10:17 6107
c_mmr_timer.S 17-Feb-2025 10:17 5720
c_mode_supervisor.S 17-Feb-2025 10:17 5667
c_mode_user.S 17-Feb-2025 10:17 6546
c_mode_user_superivsor.S 17-Feb-2025 10:17 6433
c_multi_issue_dsp_ld_ld.s 17-Feb-2025 10:17 4235
c_multi_issue_dsp_ldst_1.s 17-Feb-2025 10:17 4247
c_multi_issue_dsp_ldst_2.s 17-Feb-2025 10:17 4351
c_progctrl_call_pcpr.s 17-Feb-2025 10:17 754
c_progctrl_call_pr.s 17-Feb-2025 10:17 541
c_progctrl_clisti_interr.S 17-Feb-2025 10:17 6338
c_progctrl_csync_mmr.S 17-Feb-2025 10:17 5510
c_progctrl_except_rtx.S 17-Feb-2025 10:17 1791
c_progctrl_excpt.S 17-Feb-2025 10:17 4925
c_progctrl_jump_pcpr.s 17-Feb-2025 10:17 728
c_progctrl_jump_pr.s 17-Feb-2025 10:17 779
c_progctrl_nop.s 17-Feb-2025 10:17 642
c_progctrl_raise_rt_i_n.S 17-Feb-2025 10:17 5485
c_progctrl_rts.s 17-Feb-2025 10:17 538
c_ptr2op_pr_neg_pr.s 17-Feb-2025 10:17 3151
c_ptr2op_pr_sft_2_1.s 17-Feb-2025 10:17 3329
c_ptr2op_pr_shadd_1_2.s 17-Feb-2025 10:17 3831
c_pushpopmultiple_dp.s 17-Feb-2025 10:17 3994
c_pushpopmultiple_dp_pair.s 17-Feb-2025 10:17 3835
c_pushpopmultiple_dreg.s 17-Feb-2025 10:17 3054
c_pushpopmultiple_preg.s 17-Feb-2025 10:17 1478
c_regmv_acc_acc.s 17-Feb-2025 10:17 2252
c_regmv_dag_lz_dep.s 17-Feb-2025 10:17 1999
c_regmv_dr_acc_acc.s 17-Feb-2025 10:17 3380
c_regmv_dr_dep_nostall.s 17-Feb-2025 10:17 4167
c_regmv_dr_dr.s 17-Feb-2025 10:17 3770
c_regmv_dr_imlb.s 17-Feb-2025 10:17 8524
c_regmv_dr_pr.s 17-Feb-2025 10:17 1817
c_regmv_imlb_dep_nostall.s 17-Feb-2025 10:17 11060
c_regmv_imlb_dep_stall.s 17-Feb-2025 10:17 5625
c_regmv_imlb_dr.s 17-Feb-2025 10:17 4973
c_regmv_imlb_imlb.s 17-Feb-2025 10:17 13476
c_regmv_imlb_pr.s 17-Feb-2025 10:17 5236
c_regmv_pr_dep_nostall.s 17-Feb-2025 10:17 4681
c_regmv_pr_dep_stall.s 17-Feb-2025 10:17 4030
c_regmv_pr_dr.s 17-Feb-2025 10:17 2356
c_regmv_pr_imlb.s 17-Feb-2025 10:17 5483
c_regmv_pr_pr.s 17-Feb-2025 10:17 1775
c_seq_ac_raise_mv.S 17-Feb-2025 10:17 6516
c_seq_ac_raise_mv_ppop.S 17-Feb-2025 10:17 6835
c_seq_ac_regmv_pushpop.S 17-Feb-2025 10:17 6851
c_seq_dec_raise_pushpop.S 17-Feb-2025 10:17 6583
c_seq_ex1_brcc_mv_pop.S 17-Feb-2025 10:17 7235
c_seq_ex1_call_mv_pop.S 17-Feb-2025 10:17 7291
c_seq_ex1_j_mv_pop.S 17-Feb-2025 10:17 7126
c_seq_ex1_raise_brcc_mv_pop.S 17-Feb-2025 10:17 7214
c_seq_ex1_raise_call_mv_pop.S 17-Feb-2025 10:17 7285
c_seq_ex1_raise_j_mv_pop.S 17-Feb-2025 10:17 7121
c_seq_ex2_brcc_mp_mv_pop.S 17-Feb-2025 10:17 7255
c_seq_ex2_mmr_mvpop.S 17-Feb-2025 10:17 7512
c_seq_ex2_mmrj_mvpop.S 17-Feb-2025 10:17 7522
c_seq_ex2_raise_mmr_mvpop.S 17-Feb-2025 10:17 7480
c_seq_ex2_raise_mmrj_mvpop.S 17-Feb-2025 10:17 7518
c_seq_ex3_ls_brcc_mvp.S 17-Feb-2025 10:17 8498
c_seq_ex3_ls_mmr_mvp.S 17-Feb-2025 10:17 8487
c_seq_ex3_ls_mmrj_mvp.S 17-Feb-2025 10:17 8456
c_seq_ex3_raise_ls_mmrj_mvp.S 17-Feb-2025 10:17 8454
c_seq_wb_cs_lsmmrj_mvp.S 17-Feb-2025 10:17 8487
c_seq_wb_raisecs_lsmmrj_mvp.S 17-Feb-2025 10:17 8478
c_seq_wb_rti_lsmmrj_mvp.S 17-Feb-2025 10:17 8716
c_seq_wb_rtn_lsmmrj_mvp.S 17-Feb-2025 10:17 8568
c_seq_wb_rtx_lsmmrj_mvp.S 17-Feb-2025 10:17 9027
c_ujump.s 17-Feb-2025 10:17 621
cc-alu.S 17-Feb-2025 10:17 3495
cc-astat-bits.s 17-Feb-2025 10:17 2424
cc0.s 17-Feb-2025 10:17 369
cc1.s 17-Feb-2025 10:17 342
cc5.S 17-Feb-2025 10:17 1412
cec-exact-exception.S 17-Feb-2025 10:17 954
cec-ifetch.S 17-Feb-2025 10:17 972
cec-multi-pending.S 17-Feb-2025 10:17 3444
cec-no-snen-reti.S 17-Feb-2025 10:17 2246
cec-non-operating-env.s 17-Feb-2025 10:17 412
cec-raise-reti.S 17-Feb-2025 10:17 1820
cec-snen-reti.S 17-Feb-2025 10:17 2080
cec-syscfg-ssstep.S 17-Feb-2025 10:17 1135
cec-system-call.S 17-Feb-2025 10:17 1114
cir.s 17-Feb-2025 10:17 242
cir1.s 17-Feb-2025 10:17 2118
cli-sti.s 17-Feb-2025 10:17 350
cmpacc.s 17-Feb-2025 10:17 602
cmpdreg.S 17-Feb-2025 10:17 510
compare.s 17-Feb-2025 10:17 190
conv_enc_gen.s 17-Feb-2025 10:17 2844
cycles.s 17-Feb-2025 10:17 567
d0.s 17-Feb-2025 10:17 384
d1.s 17-Feb-2025 10:17 183
d2.s 17-Feb-2025 10:17 591
dbg_brprd_ntkn_src_kill.S 17-Feb-2025 10:17 11958
dbg_brtkn_nprd_src_kill.S 17-Feb-2025 10:17 11845
dbg_jmp_src_kill.S 17-Feb-2025 10:17 11605
dbg_tr_basic.S 17-Feb-2025 10:17 5756
dbg_tr_simplejp.S 17-Feb-2025 10:17 5561
dbg_tr_tbuf0.S 17-Feb-2025 10:17 4973
dbg_tr_umode.S 17-Feb-2025 10:17 6170
disalnexcpt_implicit.S 17-Feb-2025 10:17 3441
div0.s 17-Feb-2025 10:17 428
divq.s 17-Feb-2025 10:17 77422
dotproduct.s 17-Feb-2025 10:17 3031
dotproduct2.s 17-Feb-2025 10:17 3485
double_prec_mult.s 17-Feb-2025 10:17 1744
dsp_a4.s 17-Feb-2025 10:17 2470
dsp_a7.s 17-Feb-2025 10:17 2315
dsp_a8.s 17-Feb-2025 10:17 1777
dsp_d0.s 17-Feb-2025 10:17 403
dsp_d1.s 17-Feb-2025 10:17 1827
dsp_neg.S 17-Feb-2025 10:17 513
dsp_s1.s 17-Feb-2025 10:17 1468
e0.s 17-Feb-2025 10:17 801
edn_snafu.s 17-Feb-2025 10:17 388
eu_dsp32mac_s.s 17-Feb-2025 10:17 601
events.s 17-Feb-2025 10:17 540
f221.s 17-Feb-2025 10:17 967
fact.s 17-Feb-2025 10:17 880
fir.s 17-Feb-2025 10:17 4914
fsm.s 17-Feb-2025 10:17 698
getpid.c 17-Feb-2025 10:17 245
greg2.s 17-Feb-2025 10:17 148
hwloop-bits.S 17-Feb-2025 10:17 1476
hwloop-branch-in.s 17-Feb-2025 10:17 1910
hwloop-branch-out.s 17-Feb-2025 10:17 2096
hwloop-lt-bits.s 17-Feb-2025 10:17 317
hwloop-nested.s 17-Feb-2025 10:17 405
i0.s 17-Feb-2025 10:17 878
iir.s 17-Feb-2025 10:17 5681
issue103.s 17-Feb-2025 10:17 382
issue109.s 17-Feb-2025 10:17 281
issue112.s 17-Feb-2025 10:17 485
issue113.s 17-Feb-2025 10:17 195
issue117.s 17-Feb-2025 10:17 214
issue118.s 17-Feb-2025 10:17 415
issue119.s 17-Feb-2025 10:17 401
issue121.s 17-Feb-2025 10:17 490
issue123.s 17-Feb-2025 10:17 275
issue124.s 17-Feb-2025 10:17 280
issue125.s 17-Feb-2025 10:17 925
issue126.s 17-Feb-2025 10:17 228
issue127.s 17-Feb-2025 10:17 513
issue129.s 17-Feb-2025 10:17 413
issue139.S 17-Feb-2025 10:17 1384
issue140.S 17-Feb-2025 10:17 239
issue142.s 17-Feb-2025 10:17 469
issue144.s 17-Feb-2025 10:17 330
issue146.S 17-Feb-2025 10:17 363
issue175.s 17-Feb-2025 10:17 501
issue205.s 17-Feb-2025 10:17 1204
issue257.s 17-Feb-2025 10:17 308
issue272.S 17-Feb-2025 10:17 383
issue83.s 17-Feb-2025 10:17 1125
issue89.s 17-Feb-2025 10:17 349
l0.s 17-Feb-2025 10:17 1990
l0shift.s 17-Feb-2025 10:17 154
l2_loop.s 17-Feb-2025 10:17 271
link-2.s 17-Feb-2025 10:17 330
link.s 17-Feb-2025 10:17 995
lmu_cplb_multiple0.S 17-Feb-2025 10:17 94871
lmu_cplb_multiple1.S 17-Feb-2025 10:17 96673
lmu_excpt_align.S 17-Feb-2025 10:17 10162
lmu_excpt_default.S 17-Feb-2025 10:17 9410
lmu_excpt_illaddr.S 17-Feb-2025 10:17 10753
lmu_excpt_prot0.S 17-Feb-2025 10:17 9518
lmu_excpt_prot1.S 17-Feb-2025 10:17 9855
load.s 17-Feb-2025 10:17 4120
logic.s 17-Feb-2025 10:17 957
loop_snafu.s 17-Feb-2025 10:17 220
loop_strncpy.s 17-Feb-2025 10:17 1453
lp0.s 17-Feb-2025 10:17 237
lp1.s 17-Feb-2025 10:17 181
lsetup.s 17-Feb-2025 10:17 1128
m0boundary.s 17-Feb-2025 10:17 633
m1.S 17-Feb-2025 10:17 876
m10.s 17-Feb-2025 10:17 970
m11.s 17-Feb-2025 10:17 1157
m12.s 17-Feb-2025 10:17 1177
m13.s 17-Feb-2025 10:17 1660
m14.s 17-Feb-2025 10:17 1432
m15.s 17-Feb-2025 10:17 1417
m16.s 17-Feb-2025 10:17 1036
m17.s 17-Feb-2025 10:17 1202
m2.s 17-Feb-2025 10:17 5752
m3.s 17-Feb-2025 10:17 2626
m4.s 17-Feb-2025 10:17 2387
m5.s 17-Feb-2025 10:17 2869
m6.s 17-Feb-2025 10:17 1159
m7.s 17-Feb-2025 10:17 1403
m8.s 17-Feb-2025 10:17 1042
m9.s 17-Feb-2025 10:17 1470
mac2halfreg.S 17-Feb-2025 10:17 332
math.s 17-Feb-2025 10:17 819
max_min_flags.s 17-Feb-2025 10:17 3683
mc_s2.s 17-Feb-2025 10:17 1346
mdma-32bit-1d-neg-count.c 17-Feb-2025 10:17 466
mdma-32bit-1d.c 17-Feb-2025 10:17 391
mdma-8bit-1d-neg-count.c 17-Feb-2025 10:17 466
mdma-8bit-1d.c 17-Feb-2025 10:17 391
mdma-skel.h 17-Feb-2025 10:17 1627
mem3.s 17-Feb-2025 10:17 481
mmr-exception.s 17-Feb-2025 10:17 620
move.s 17-Feb-2025 10:17 560
msa_acp_5.10.S 17-Feb-2025 10:17 487
msa_acp_5.12_1.S 17-Feb-2025 10:17 1012
msa_acp_5.12_2.S 17-Feb-2025 10:17 793
msa_acp_5_10.s 17-Feb-2025 10:17 760
mult.s 17-Feb-2025 10:17 268
neg-2.S 17-Feb-2025 10:17 796
neg-3.S 17-Feb-2025 10:17 784
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run-tests.sh 17-Feb-2025 10:17 5392
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