Index of /build/tmp/work/x86_64-nativesdk-tdxsdk-linux/nativesdk-glibc/2.35-r0/git/sysdeps/x86_64/fpu/multiarch/


../
Makefile                                           17-Feb-2025 10:16                3086
e_asin-fma.c                                       17-Feb-2025 10:16                 302
e_asin-fma4.c                                      17-Feb-2025 10:16                 309
e_asin.c                                           17-Feb-2025 10:16                1505
e_atan2-avx.c                                      17-Feb-2025 10:16                 271
e_atan2-fma.c                                      17-Feb-2025 10:16                 303
e_atan2-fma4.c                                     17-Feb-2025 10:16                 311
e_atan2.c                                          17-Feb-2025 10:16                1212
e_exp-avx.c                                        17-Feb-2025 10:16                 149
e_exp-fma.c                                        17-Feb-2025 10:16                 149
e_exp-fma4.c                                       17-Feb-2025 10:16                 151
e_exp.c                                            17-Feb-2025 10:16                1195
e_exp2f-fma.c                                      17-Feb-2025 10:16                  73
e_exp2f.c                                          17-Feb-2025 10:16                1354
e_expf-fma.c                                       17-Feb-2025 10:16                  70
e_expf.c                                           17-Feb-2025 10:16                1433
e_log-avx.c                                        17-Feb-2025 10:16                 149
e_log-fma.c                                        17-Feb-2025 10:16                 149
e_log-fma4.c                                       17-Feb-2025 10:16                 151
e_log.c                                            17-Feb-2025 10:16                1195
e_log2-fma.c                                       17-Feb-2025 10:16                  70
e_log2.c                                           17-Feb-2025 10:16                1437
e_log2f-fma.c                                      17-Feb-2025 10:16                  73
e_log2f.c                                          17-Feb-2025 10:16                1454
e_logf-fma.c                                       17-Feb-2025 10:16                  70
e_logf.c                                           17-Feb-2025 10:16                1433
e_pow-fma.c                                        17-Feb-2025 10:16                 149
e_pow-fma4.c                                       17-Feb-2025 10:16                 151
e_pow.c                                            17-Feb-2025 10:16                1199
e_powf-fma.c                                       17-Feb-2025 10:16                  70
e_powf.c                                           17-Feb-2025 10:16                1490
ifunc-avx-fma4.h                                   17-Feb-2025 10:16                1583
ifunc-fma.h                                        17-Feb-2025 10:16                1281
ifunc-fma4.h                                       17-Feb-2025 10:16                1437
ifunc-mathvec-avx2.h                               17-Feb-2025 10:16                1386
ifunc-mathvec-avx512-skx.h                         17-Feb-2025 10:16                1415
ifunc-mathvec-avx512.h                             17-Feb-2025 10:16                1570
ifunc-mathvec-sse4_1.h                             17-Feb-2025 10:16                1326
ifunc-sse4_1.h                                     17-Feb-2025 10:16                1229
s_atan-avx.c                                       17-Feb-2025 10:16                 228
s_atan-fma.c                                       17-Feb-2025 10:16                 258
s_atan-fma4.c                                      17-Feb-2025 10:16                 265
s_atan.c                                           17-Feb-2025 10:16                1119
s_ceil-c.c                                         17-Feb-2025 10:16                  67
s_ceil-sse4_1.S                                    17-Feb-2025 10:16                 919
s_ceil.c                                           17-Feb-2025 10:16                1139
s_ceilf-c.c                                        17-Feb-2025 10:16                  70
s_ceilf-sse4_1.S                                   17-Feb-2025 10:16                 921
s_ceilf.c                                          17-Feb-2025 10:16                1147
s_cosf-fma.c                                       17-Feb-2025 10:16                  67
s_cosf-sse2.c                                      17-Feb-2025 10:16                  68
s_cosf.c                                           17-Feb-2025 10:16                1038
s_expm1-fma.c                                      17-Feb-2025 10:16                 302
s_expm1.c                                          17-Feb-2025 10:16                1293
s_floor-c.c                                        17-Feb-2025 10:16                  85
s_floor-sse4_1.S                                   17-Feb-2025 10:16                 920
s_floor.c                                          17-Feb-2025 10:16                1151
s_floorf-c.c                                       17-Feb-2025 10:16                  89
s_floorf-sse4_1.S                                  17-Feb-2025 10:16                 922
s_floorf.c                                         17-Feb-2025 10:16                1159
s_fma.c                                            17-Feb-2025 10:16                1693
s_fmaf.c                                           17-Feb-2025 10:16                1527
s_log1p-fma.c                                      17-Feb-2025 10:16                 129
s_log1p.c                                          17-Feb-2025 10:16                1084
s_nearbyint-c.c                                    17-Feb-2025 10:16                 101
s_nearbyint-sse4_1.S                               17-Feb-2025 10:16                 930
s_nearbyint.c                                      17-Feb-2025 10:16                1183
s_nearbyintf-c.c                                   17-Feb-2025 10:16                 105
s_nearbyintf-sse4_1.S                              17-Feb-2025 10:16                 932
s_nearbyintf.c                                     17-Feb-2025 10:16                1191
s_rint-c.c                                         17-Feb-2025 10:16                  81
s_rint-sse4_1.S                                    17-Feb-2025 10:16                 918
s_rint.c                                           17-Feb-2025 10:16                1139
s_rintf-c.c                                        17-Feb-2025 10:16                  85
s_rintf-sse4_1.S                                   17-Feb-2025 10:16                 920
s_rintf.c                                          17-Feb-2025 10:16                1147
s_roundeven-c.c                                    17-Feb-2025 10:16                  82
s_roundeven-sse4_1.S                               17-Feb-2025 10:16                 928
s_roundeven.c                                      17-Feb-2025 10:16                1174
s_roundevenf-c.c                                   17-Feb-2025 10:16                 105
s_roundevenf-sse4_1.S                              17-Feb-2025 10:16                 930
s_roundevenf.c                                     17-Feb-2025 10:16                1182
s_sin-avx.c                                        17-Feb-2025 10:16                 147
s_sin-fma.c                                        17-Feb-2025 10:16                 321
s_sin-fma4.c                                       17-Feb-2025 10:16                 330
s_sin.c                                            17-Feb-2025 10:16                1351
s_sincosf-fma.c                                    17-Feb-2025 10:16                  76
s_sincosf-sse2.c                                   17-Feb-2025 10:16                  77
s_sincosf.c                                        17-Feb-2025 10:16                1076
s_sinf-fma.c                                       17-Feb-2025 10:16                  67
s_sinf-sse2.c                                      17-Feb-2025 10:16                  68
s_sinf.c                                           17-Feb-2025 10:16                1038
s_tan-avx.c                                        17-Feb-2025 10:16                 177
s_tan-fma.c                                        17-Feb-2025 10:16                 239
s_tan-fma4.c                                       17-Feb-2025 10:16                 245
s_tan.c                                            17-Feb-2025 10:16                1109
s_trunc-c.c                                        17-Feb-2025 10:16                  70
s_trunc-sse4_1.S                                   17-Feb-2025 10:16                 942
s_trunc.c                                          17-Feb-2025 10:16                1151
s_truncf-c.c                                       17-Feb-2025 10:16                  73
s_truncf-sse4_1.S                                  17-Feb-2025 10:16                 945
s_truncf.c                                         17-Feb-2025 10:16                1159
svml_d_acos2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_acos2_core.c                                17-Feb-2025 10:16                1132
svml_d_acos2_core_sse4.S                           17-Feb-2025 10:16               10475
svml_d_acos4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_acos4_core.c                                17-Feb-2025 10:16                1130
svml_d_acos4_core_avx2.S                           17-Feb-2025 10:16               12264
svml_d_acos8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_acos8_core.c                                17-Feb-2025 10:16                1136
svml_d_acos8_core_avx512.S                         17-Feb-2025 10:16               15272
svml_d_acosh2_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_acosh2_core.c                               17-Feb-2025 10:16                1137
svml_d_acosh2_core_sse4.S                          17-Feb-2025 10:16               59678
svml_d_acosh4_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_acosh4_core.c                               17-Feb-2025 10:16                1135
svml_d_acosh4_core_avx2.S                          17-Feb-2025 10:16               63704
svml_d_acosh8_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_acosh8_core.c                               17-Feb-2025 10:16                1141
svml_d_acosh8_core_avx512.S                        17-Feb-2025 10:16               20521
svml_d_asin2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_asin2_core.c                                17-Feb-2025 10:16                1132
svml_d_asin2_core_sse4.S                           17-Feb-2025 10:16                9994
svml_d_asin4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_asin4_core.c                                17-Feb-2025 10:16                1130
svml_d_asin4_core_avx2.S                           17-Feb-2025 10:16               11794
svml_d_asin8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_asin8_core.c                                17-Feb-2025 10:16                1136
svml_d_asin8_core_avx512.S                         17-Feb-2025 10:16               14710
svml_d_asinh2_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_asinh2_core.c                               17-Feb-2025 10:16                1137
svml_d_asinh2_core_sse4.S                          17-Feb-2025 10:16               66450
svml_d_asinh4_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_asinh4_core.c                               17-Feb-2025 10:16                1135
svml_d_asinh4_core_avx2.S                          17-Feb-2025 10:16               66331
svml_d_asinh8_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_asinh8_core.c                               17-Feb-2025 10:16                1141
svml_d_asinh8_core_avx512.S                        17-Feb-2025 10:16               21415
svml_d_atan22_core-sse2.S                          17-Feb-2025 10:16                 907
svml_d_atan22_core.c                               17-Feb-2025 10:16                1149
svml_d_atan22_core_sse4.S                          17-Feb-2025 10:16               16105
svml_d_atan24_core-sse.S                           17-Feb-2025 10:16                 913
svml_d_atan24_core.c                               17-Feb-2025 10:16                1147
svml_d_atan24_core_avx2.S                          17-Feb-2025 10:16               18276
svml_d_atan28_core-avx2.S                          17-Feb-2025 10:16                 915
svml_d_atan28_core.c                               17-Feb-2025 10:16                1153
svml_d_atan28_core_avx512.S                        17-Feb-2025 10:16               21621
svml_d_atan2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_atan2_core.c                                17-Feb-2025 10:16                1132
svml_d_atan2_core_sse4.S                           17-Feb-2025 10:16                9590
svml_d_atan4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_atan4_core.c                                17-Feb-2025 10:16                1130
svml_d_atan4_core_avx2.S                           17-Feb-2025 10:16                9981
svml_d_atan8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_atan8_core.c                                17-Feb-2025 10:16                1136
svml_d_atan8_core_avx512.S                         17-Feb-2025 10:16               10611
svml_d_atanh2_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_atanh2_core.c                               17-Feb-2025 10:16                1137
svml_d_atanh2_core_sse4.S                          17-Feb-2025 10:16               61216
svml_d_atanh4_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_atanh4_core.c                               17-Feb-2025 10:16                1135
svml_d_atanh4_core_avx2.S                          17-Feb-2025 10:16               61377
svml_d_atanh8_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_atanh8_core.c                               17-Feb-2025 10:16                1141
svml_d_atanh8_core_avx512.S                        17-Feb-2025 10:16               16574
svml_d_cbrt2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_cbrt2_core.c                                17-Feb-2025 10:16                1132
svml_d_cbrt2_core_sse4.S                           17-Feb-2025 10:16               21943
svml_d_cbrt4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_cbrt4_core.c                                17-Feb-2025 10:16                1130
svml_d_cbrt4_core_avx2.S                           17-Feb-2025 10:16               25211
svml_d_cbrt8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_cbrt8_core.c                                17-Feb-2025 10:16                1136
svml_d_cbrt8_core_avx512.S                         17-Feb-2025 10:16               11554
svml_d_cos2_core-sse2.S                            17-Feb-2025 10:16                 917
svml_d_cos2_core.c                                 17-Feb-2025 10:16                1127
svml_d_cos2_core_sse4.S                            17-Feb-2025 10:16                6321
svml_d_cos4_core-sse.S                             17-Feb-2025 10:16                 923
svml_d_cos4_core.c                                 17-Feb-2025 10:16                1125
svml_d_cos4_core_avx2.S                            17-Feb-2025 10:16                5903
svml_d_cos8_core-avx2.S                            17-Feb-2025 10:16                 925
svml_d_cos8_core.c                                 17-Feb-2025 10:16                1127
svml_d_cos8_core_avx512.S                          17-Feb-2025 10:16               13068
svml_d_cosh2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_cosh2_core.c                                17-Feb-2025 10:16                1132
svml_d_cosh2_core_sse4.S                           17-Feb-2025 10:16               15909
svml_d_cosh4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_cosh4_core.c                                17-Feb-2025 10:16                1130
svml_d_cosh4_core_avx2.S                           17-Feb-2025 10:16               18318
svml_d_cosh8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_cosh8_core.c                                17-Feb-2025 10:16                1136
svml_d_cosh8_core_avx512.S                         17-Feb-2025 10:16               14807
svml_d_erf2_core-sse2.S                            17-Feb-2025 10:16                 917
svml_d_erf2_core.c                                 17-Feb-2025 10:16                1127
svml_d_erf2_core_sse4.S                            17-Feb-2025 10:16               48294
svml_d_erf4_core-sse.S                             17-Feb-2025 10:16                 923
svml_d_erf4_core.c                                 17-Feb-2025 10:16                1125
svml_d_erf4_core_avx2.S                            17-Feb-2025 10:16               49195
svml_d_erf8_core-avx2.S                            17-Feb-2025 10:16                 925
svml_d_erf8_core.c                                 17-Feb-2025 10:16                1131
svml_d_erf8_core_avx512.S                          17-Feb-2025 10:16               50574
svml_d_erfc2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_erfc2_core.c                                17-Feb-2025 10:16                1132
svml_d_erfc2_core_sse4.S                           17-Feb-2025 10:16              197879
svml_d_erfc4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_erfc4_core.c                                17-Feb-2025 10:16                1130
svml_d_erfc4_core_avx2.S                           17-Feb-2025 10:16              200637
svml_d_erfc8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_erfc8_core.c                                17-Feb-2025 10:16                1136
svml_d_erfc8_core_avx512.S                         17-Feb-2025 10:16              203215
svml_d_exp102_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_exp102_core.c                               17-Feb-2025 10:16                1137
svml_d_exp102_core_sse4.S                          17-Feb-2025 10:16               16090
svml_d_exp104_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_exp104_core.c                               17-Feb-2025 10:16                1135
svml_d_exp104_core_avx2.S                          17-Feb-2025 10:16               18252
svml_d_exp108_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_exp108_core.c                               17-Feb-2025 10:16                1141
svml_d_exp108_core_avx512.S                        17-Feb-2025 10:16               12744
svml_d_exp22_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_exp22_core.c                                17-Feb-2025 10:16                1132
svml_d_exp22_core_sse4.S                           17-Feb-2025 10:16               13227
svml_d_exp24_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_exp24_core.c                                17-Feb-2025 10:16                1130
svml_d_exp24_core_avx2.S                           17-Feb-2025 10:16               15319
svml_d_exp28_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_exp28_core.c                                17-Feb-2025 10:16                1136
svml_d_exp28_core_avx512.S                         17-Feb-2025 10:16               12146
svml_d_exp2_core-sse2.S                            17-Feb-2025 10:16                 897
svml_d_exp2_core.c                                 17-Feb-2025 10:16                1127
svml_d_exp2_core_sse4.S                            17-Feb-2025 10:16                6361
svml_d_exp4_core-sse.S                             17-Feb-2025 10:16                 903
svml_d_exp4_core.c                                 17-Feb-2025 10:16                1125
svml_d_exp4_core_avx2.S                            17-Feb-2025 10:16                6198
svml_d_exp8_core-avx2.S                            17-Feb-2025 10:16                 905
svml_d_exp8_core.c                                 17-Feb-2025 10:16                1127
svml_d_exp8_core_avx512.S                          17-Feb-2025 10:16               13547
svml_d_expm12_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_expm12_core.c                               17-Feb-2025 10:16                1137
svml_d_expm12_core_sse4.S                          17-Feb-2025 10:16               17267
svml_d_expm14_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_expm14_core.c                               17-Feb-2025 10:16                1135
svml_d_expm14_core_avx2.S                          17-Feb-2025 10:16               17702
svml_d_expm18_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_expm18_core.c                               17-Feb-2025 10:16                1141
svml_d_expm18_core_avx512.S                        17-Feb-2025 10:16               14671
svml_d_hypot2_core-sse2.S                          17-Feb-2025 10:16                 907
svml_d_hypot2_core.c                               17-Feb-2025 10:16                1149
svml_d_hypot2_core_sse4.S                          17-Feb-2025 10:16                9103
svml_d_hypot4_core-sse.S                           17-Feb-2025 10:16                 913
svml_d_hypot4_core.c                               17-Feb-2025 10:16                1147
svml_d_hypot4_core_avx2.S                          17-Feb-2025 10:16               11086
svml_d_hypot8_core-avx2.S                          17-Feb-2025 10:16                 915
svml_d_hypot8_core.c                               17-Feb-2025 10:16                1153
svml_d_hypot8_core_avx512.S                        17-Feb-2025 10:16                9110
svml_d_log102_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_log102_core.c                               17-Feb-2025 10:16                1137
svml_d_log102_core_sse4.S                          17-Feb-2025 10:16               41840
svml_d_log104_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_log104_core.c                               17-Feb-2025 10:16                1135
svml_d_log104_core_avx2.S                          17-Feb-2025 10:16               42191
svml_d_log108_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_log108_core.c                               17-Feb-2025 10:16                1141
svml_d_log108_core_avx512.S                        17-Feb-2025 10:16               12465
svml_d_log1p2_core-sse2.S                          17-Feb-2025 10:16                 925
svml_d_log1p2_core.c                               17-Feb-2025 10:16                1137
svml_d_log1p2_core_sse4.S                          17-Feb-2025 10:16               57126
svml_d_log1p4_core-sse.S                           17-Feb-2025 10:16                 931
svml_d_log1p4_core.c                               17-Feb-2025 10:16                1135
svml_d_log1p4_core_avx2.S                          17-Feb-2025 10:16               57758
svml_d_log1p8_core-avx2.S                          17-Feb-2025 10:16                 933
svml_d_log1p8_core.c                               17-Feb-2025 10:16                1141
svml_d_log1p8_core_avx512.S                        17-Feb-2025 10:16               13111
svml_d_log22_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_log22_core.c                                17-Feb-2025 10:16                1132
svml_d_log22_core_sse4.S                           17-Feb-2025 10:16               55123
svml_d_log24_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_log24_core.c                                17-Feb-2025 10:16                1130
svml_d_log24_core_avx2.S                           17-Feb-2025 10:16               55430
svml_d_log28_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_log28_core.c                                17-Feb-2025 10:16                1136
svml_d_log28_core_avx512.S                         17-Feb-2025 10:16               12058
svml_d_log2_core-sse2.S                            17-Feb-2025 10:16                 897
svml_d_log2_core.c                                 17-Feb-2025 10:16                1127
svml_d_log2_core_sse4.S                            17-Feb-2025 10:16                6596
svml_d_log4_core-sse.S                             17-Feb-2025 10:16                 903
svml_d_log4_core.c                                 17-Feb-2025 10:16                1125
svml_d_log4_core_avx2.S                            17-Feb-2025 10:16                6226
svml_d_log8_core-avx2.S                            17-Feb-2025 10:16                 905
svml_d_log8_core.c                                 17-Feb-2025 10:16                1127
svml_d_log8_core_avx512.S                          17-Feb-2025 10:16               13913
svml_d_pow2_core-sse2.S                            17-Feb-2025 10:16                 899
svml_d_pow2_core.c                                 17-Feb-2025 10:16                1139
svml_d_pow2_core_sse4.S                            17-Feb-2025 10:16               12571
svml_d_pow4_core-sse.S                             17-Feb-2025 10:16                 905
svml_d_pow4_core.c                                 17-Feb-2025 10:16                1137
svml_d_pow4_core_avx2.S                            17-Feb-2025 10:16               11908
svml_d_pow8_core-avx2.S                            17-Feb-2025 10:16                 907
svml_d_pow8_core.c                                 17-Feb-2025 10:16                1139
svml_d_pow8_core_avx512.S                          17-Feb-2025 10:16               22501
svml_d_sin2_core-sse2.S                            17-Feb-2025 10:16                 897
svml_d_sin2_core.c                                 17-Feb-2025 10:16                1127
svml_d_sin2_core_sse4.S                            17-Feb-2025 10:16                6284
svml_d_sin4_core-sse.S                             17-Feb-2025 10:16                 923
svml_d_sin4_core.c                                 17-Feb-2025 10:16                1125
svml_d_sin4_core_avx2.S                            17-Feb-2025 10:16                5893
svml_d_sin8_core-avx2.S                            17-Feb-2025 10:16                 926
svml_d_sin8_core.c                                 17-Feb-2025 10:16                1127
svml_d_sin8_core_avx512.S                          17-Feb-2025 10:16               13044
svml_d_sincos2_core-sse2.S                         17-Feb-2025 10:16                 913
svml_d_sincos2_core.c                              17-Feb-2025 10:16                1158
svml_d_sincos2_core_sse4.S                         17-Feb-2025 10:16               10286
svml_d_sincos4_core-sse.S                          17-Feb-2025 10:16                 919
svml_d_sincos4_core.c                              17-Feb-2025 10:16                1156
svml_d_sincos4_core_avx2.S                         17-Feb-2025 10:16               10809
svml_d_sincos8_core-avx2.S                         17-Feb-2025 10:16                 921
svml_d_sincos8_core.c                              17-Feb-2025 10:16                1158
svml_d_sincos8_core_avx512.S                       17-Feb-2025 10:16               21510
svml_d_sinh2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_sinh2_core.c                                17-Feb-2025 10:16                1132
svml_d_sinh2_core_sse4.S                           17-Feb-2025 10:16               23276
svml_d_sinh4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_sinh4_core.c                                17-Feb-2025 10:16                1130
svml_d_sinh4_core_avx2.S                           17-Feb-2025 10:16               25503
svml_d_sinh8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_sinh8_core.c                                17-Feb-2025 10:16                1136
svml_d_sinh8_core_avx512.S                         17-Feb-2025 10:16               26289
svml_d_tan2_core-sse2.S                            17-Feb-2025 10:16                 917
svml_d_tan2_core.c                                 17-Feb-2025 10:16                1127
svml_d_tan2_core_sse4.S                            17-Feb-2025 10:16              368772
svml_d_tan4_core-sse.S                             17-Feb-2025 10:16                 923
svml_d_tan4_core.c                                 17-Feb-2025 10:16                1125
svml_d_tan4_core_avx2.S                            17-Feb-2025 10:16              372467
svml_d_tan8_core-avx2.S                            17-Feb-2025 10:16                 925
svml_d_tan8_core.c                                 17-Feb-2025 10:16                1131
svml_d_tan8_core_avx512.S                          17-Feb-2025 10:16              198860
svml_d_tanh2_core-sse2.S                           17-Feb-2025 10:16                 921
svml_d_tanh2_core.c                                17-Feb-2025 10:16                1132
svml_d_tanh2_core_sse4.S                           17-Feb-2025 10:16               79540
svml_d_tanh4_core-sse.S                            17-Feb-2025 10:16                 927
svml_d_tanh4_core.c                                17-Feb-2025 10:16                1130
svml_d_tanh4_core_avx2.S                           17-Feb-2025 10:16               81673
svml_d_tanh8_core-avx2.S                           17-Feb-2025 10:16                 929
svml_d_tanh8_core.c                                17-Feb-2025 10:16                1136
svml_d_tanh8_core_avx512.S                         17-Feb-2025 10:16               24575
svml_s_acosf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_acosf16_core.c                              17-Feb-2025 10:16                1154
svml_s_acosf16_core_avx512.S                       17-Feb-2025 10:16               12481
svml_s_acosf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_acosf4_core.c                               17-Feb-2025 10:16                1145
svml_s_acosf4_core_sse4.S                          17-Feb-2025 10:16                8693
svml_s_acosf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_acosf8_core.c                               17-Feb-2025 10:16                1143
svml_s_acosf8_core_avx2.S                          17-Feb-2025 10:16               10528
svml_s_acoshf16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_acoshf16_core.c                             17-Feb-2025 10:16                1159
svml_s_acoshf16_core_avx512.S                      17-Feb-2025 10:16               17618
svml_s_acoshf4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_acoshf4_core.c                              17-Feb-2025 10:16                1150
svml_s_acoshf4_core_sse4.S                         17-Feb-2025 10:16               13146
svml_s_acoshf8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_acoshf8_core.c                              17-Feb-2025 10:16                1148
svml_s_acoshf8_core_avx2.S                         17-Feb-2025 10:16               14990
svml_s_asinf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_asinf16_core.c                              17-Feb-2025 10:16                1154
svml_s_asinf16_core_avx512.S                       17-Feb-2025 10:16               11902
svml_s_asinf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_asinf4_core.c                               17-Feb-2025 10:16                1145
svml_s_asinf4_core_sse4.S                          17-Feb-2025 10:16                8189
svml_s_asinf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_asinf8_core.c                               17-Feb-2025 10:16                1143
svml_s_asinf8_core_avx2.S                          17-Feb-2025 10:16               10028
svml_s_asinhf16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_asinhf16_core.c                             17-Feb-2025 10:16                1159
svml_s_asinhf16_core_avx512.S                      17-Feb-2025 10:16               18472
svml_s_asinhf4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_asinhf4_core.c                              17-Feb-2025 10:16                1150
svml_s_asinhf4_core_sse4.S                         17-Feb-2025 10:16               17383
svml_s_asinhf8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_asinhf8_core.c                              17-Feb-2025 10:16                1148
svml_s_asinhf8_core_avx2.S                         17-Feb-2025 10:16               18465
svml_s_atan2f16_core-avx2.S                        17-Feb-2025 10:16                 922
svml_s_atan2f16_core.c                             17-Feb-2025 10:16                1163
svml_s_atan2f16_core_avx512.S                      17-Feb-2025 10:16               17602
svml_s_atan2f4_core-sse2.S                         17-Feb-2025 10:16                 911
svml_s_atan2f4_core.c                              17-Feb-2025 10:16                1154
svml_s_atan2f4_core_sse4.S                         17-Feb-2025 10:16               12645
svml_s_atan2f8_core-sse.S                          17-Feb-2025 10:16                 918
svml_s_atan2f8_core.c                              17-Feb-2025 10:16                1150
svml_s_atan2f8_core_avx2.S                         17-Feb-2025 10:16               14203
svml_s_atanf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_atanf16_core.c                              17-Feb-2025 10:16                1154
svml_s_atanf16_core_avx512.S                       17-Feb-2025 10:16                8595
svml_s_atanf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_atanf4_core.c                               17-Feb-2025 10:16                1145
svml_s_atanf4_core_sse4.S                          17-Feb-2025 10:16                6365
svml_s_atanf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_atanf8_core.c                               17-Feb-2025 10:16                1143
svml_s_atanf8_core_avx2.S                          17-Feb-2025 10:16                6690
svml_s_atanhf16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_atanhf16_core.c                             17-Feb-2025 10:16                1159
svml_s_atanhf16_core_avx512.S                      17-Feb-2025 10:16               14960
svml_s_atanhf4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_atanhf4_core.c                              17-Feb-2025 10:16                1150
svml_s_atanhf4_core_sse4.S                         17-Feb-2025 10:16               12148
svml_s_atanhf8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_atanhf8_core.c                              17-Feb-2025 10:16                1148
svml_s_atanhf8_core_avx2.S                         17-Feb-2025 10:16               13585
svml_s_cbrtf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_cbrtf16_core.c                              17-Feb-2025 10:16                1154
svml_s_cbrtf16_core_avx512.S                       17-Feb-2025 10:16                9208
svml_s_cbrtf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_cbrtf4_core.c                               17-Feb-2025 10:16                1145
svml_s_cbrtf4_core_sse4.S                          17-Feb-2025 10:16               20768
svml_s_cbrtf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_cbrtf8_core.c                               17-Feb-2025 10:16                1143
svml_s_cbrtf8_core_avx2.S                          17-Feb-2025 10:16               23702
svml_s_cosf16_core-avx2.S                          17-Feb-2025 10:16                 912
svml_s_cosf16_core.c                               17-Feb-2025 10:16                1145
svml_s_cosf16_core_avx512.S                        17-Feb-2025 10:16               14354
svml_s_cosf4_core-sse2.S                           17-Feb-2025 10:16                 921
svml_s_cosf4_core.c                                17-Feb-2025 10:16                1140
svml_s_cosf4_core_sse4.S                           17-Feb-2025 10:16                6837
svml_s_cosf8_core-sse.S                            17-Feb-2025 10:16                 928
svml_s_cosf8_core.c                                17-Feb-2025 10:16                1138
svml_s_cosf8_core_avx2.S                           17-Feb-2025 10:16                6538
svml_s_coshf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_coshf16_core.c                              17-Feb-2025 10:16                1154
svml_s_coshf16_core_avx512.S                       17-Feb-2025 10:16               14498
svml_s_coshf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_coshf4_core.c                               17-Feb-2025 10:16                1145
svml_s_coshf4_core_sse4.S                          17-Feb-2025 10:16                9344
svml_s_coshf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_coshf8_core.c                               17-Feb-2025 10:16                1143
svml_s_coshf8_core_avx2.S                          17-Feb-2025 10:16               11338
svml_s_erfcf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_erfcf16_core.c                              17-Feb-2025 10:16                1154
svml_s_erfcf16_core_avx512.S                       17-Feb-2025 10:16               36776
svml_s_erfcf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_erfcf4_core.c                               17-Feb-2025 10:16                1145
svml_s_erfcf4_core_sse4.S                          17-Feb-2025 10:16               33597
svml_s_erfcf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_erfcf8_core.c                               17-Feb-2025 10:16                1143
svml_s_erfcf8_core_avx2.S                          17-Feb-2025 10:16               36156
svml_s_erff16_core-avx2.S                          17-Feb-2025 10:16                 912
svml_s_erff16_core.c                               17-Feb-2025 10:16                1149
svml_s_erff16_core_avx512.S                        17-Feb-2025 10:16                9963
svml_s_erff4_core-sse2.S                           17-Feb-2025 10:16                 921
svml_s_erff4_core.c                                17-Feb-2025 10:16                1140
svml_s_erff4_core_sse4.S                           17-Feb-2025 10:16               23765
svml_s_erff8_core-sse.S                            17-Feb-2025 10:16                 928
svml_s_erff8_core.c                                17-Feb-2025 10:16                1138
svml_s_erff8_core_avx2.S                           17-Feb-2025 10:16               24365
svml_s_exp10f16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_exp10f16_core.c                             17-Feb-2025 10:16                1159
svml_s_exp10f16_core_avx512.S                      17-Feb-2025 10:16               12160
svml_s_exp10f4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_exp10f4_core.c                              17-Feb-2025 10:16                1150
svml_s_exp10f4_core_sse4.S                         17-Feb-2025 10:16               10149
svml_s_exp10f8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_exp10f8_core.c                              17-Feb-2025 10:16                1148
svml_s_exp10f8_core_avx2.S                         17-Feb-2025 10:16               12560
svml_s_exp2f16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_exp2f16_core.c                              17-Feb-2025 10:16                1154
svml_s_exp2f16_core_avx512.S                       17-Feb-2025 10:16               10241
svml_s_exp2f4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_exp2f4_core.c                               17-Feb-2025 10:16                1145
svml_s_exp2f4_core_sse4.S                          17-Feb-2025 10:16                7436
svml_s_exp2f8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_exp2f8_core.c                               17-Feb-2025 10:16                1143
svml_s_exp2f8_core_avx2.S                          17-Feb-2025 10:16                9334
svml_s_expf16_core-avx2.S                          17-Feb-2025 10:16                 933
svml_s_expf16_core.c                               17-Feb-2025 10:16                1145
svml_s_expf16_core_avx512.S                        17-Feb-2025 10:16               12634
svml_s_expf4_core-sse2.S                           17-Feb-2025 10:16                 901
svml_s_expf4_core.c                                17-Feb-2025 10:16                1140
svml_s_expf4_core_sse4.S                           17-Feb-2025 10:16                5895
svml_s_expf8_core-sse.S                            17-Feb-2025 10:16                 908
svml_s_expf8_core.c                                17-Feb-2025 10:16                1138
svml_s_expf8_core_avx2.S                           17-Feb-2025 10:16                5709
svml_s_expm1f16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_expm1f16_core.c                             17-Feb-2025 10:16                1159
svml_s_expm1f16_core_avx512.S                      17-Feb-2025 10:16               12657
svml_s_expm1f4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_expm1f4_core.c                              17-Feb-2025 10:16                1150
svml_s_expm1f4_core_sse4.S                         17-Feb-2025 10:16               12914
svml_s_expm1f8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_expm1f8_core.c                              17-Feb-2025 10:16                1148
svml_s_expm1f8_core_avx2.S                         17-Feb-2025 10:16               13567
svml_s_hypotf16_core-avx2.S                        17-Feb-2025 10:16                 922
svml_s_hypotf16_core.c                             17-Feb-2025 10:16                1163
svml_s_hypotf16_core_avx512.S                      17-Feb-2025 10:16                9032
svml_s_hypotf4_core-sse2.S                         17-Feb-2025 10:16                 911
svml_s_hypotf4_core.c                              17-Feb-2025 10:16                1154
svml_s_hypotf4_core_sse4.S                         17-Feb-2025 10:16                8053
svml_s_hypotf8_core-sse.S                          17-Feb-2025 10:16                 918
svml_s_hypotf8_core.c                              17-Feb-2025 10:16                1150
svml_s_hypotf8_core_avx2.S                         17-Feb-2025 10:16                9610
svml_s_log10f16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_log10f16_core.c                             17-Feb-2025 10:16                1159
svml_s_log10f16_core_avx512.S                      17-Feb-2025 10:16                8945
svml_s_log10f4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_log10f4_core.c                              17-Feb-2025 10:16                1150
svml_s_log10f4_core_sse4.S                         17-Feb-2025 10:16                8313
svml_s_log10f8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_log10f8_core.c                              17-Feb-2025 10:16                1148
svml_s_log10f8_core_avx2.S                         17-Feb-2025 10:16               10405
svml_s_log1pf16_core-avx2.S                        17-Feb-2025 10:16                 920
svml_s_log1pf16_core.c                             17-Feb-2025 10:16                1159
svml_s_log1pf16_core_avx512.S                      17-Feb-2025 10:16               13103
svml_s_log1pf4_core-sse2.S                         17-Feb-2025 10:16                 929
svml_s_log1pf4_core.c                              17-Feb-2025 10:16                1150
svml_s_log1pf4_core_sse4.S                         17-Feb-2025 10:16                8694
svml_s_log1pf8_core-sse.S                          17-Feb-2025 10:16                 936
svml_s_log1pf8_core.c                              17-Feb-2025 10:16                1148
svml_s_log1pf8_core_avx2.S                         17-Feb-2025 10:16               10804
svml_s_log2f16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_log2f16_core.c                              17-Feb-2025 10:16                1154
svml_s_log2f16_core_avx512.S                       17-Feb-2025 10:16                8455
svml_s_log2f4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_log2f4_core.c                               17-Feb-2025 10:16                1145
svml_s_log2f4_core_sse4.S                          17-Feb-2025 10:16                7473
svml_s_log2f8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_log2f8_core.c                               17-Feb-2025 10:16                1143
svml_s_log2f8_core_avx2.S                          17-Feb-2025 10:16                9495
svml_s_logf16_core-avx2.S                          17-Feb-2025 10:16                 912
svml_s_logf16_core.c                               17-Feb-2025 10:16                1145
svml_s_logf16_core_avx512.S                        17-Feb-2025 10:16               12311
svml_s_logf4_core-sse2.S                           17-Feb-2025 10:16                 901
svml_s_logf4_core.c                                17-Feb-2025 10:16                1140
svml_s_logf4_core_sse4.S                           17-Feb-2025 10:16                5696
svml_s_logf8_core-sse.S                            17-Feb-2025 10:16                 908
svml_s_logf8_core.c                                17-Feb-2025 10:16                1138
svml_s_logf8_core_avx2.S                           17-Feb-2025 10:16                5548
svml_s_powf16_core-avx2.S                          17-Feb-2025 10:16                 914
svml_s_powf16_core.c                               17-Feb-2025 10:16                1149
svml_s_powf16_core_avx512.S                        17-Feb-2025 10:16               21610
svml_s_powf4_core-sse2.S                           17-Feb-2025 10:16                 903
svml_s_powf4_core.c                                17-Feb-2025 10:16                1144
svml_s_powf4_core_sse4.S                           17-Feb-2025 10:16               11844
svml_s_powf8_core-sse.S                            17-Feb-2025 10:16                 910
svml_s_powf8_core.c                                17-Feb-2025 10:16                1142
svml_s_powf8_core_avx2.S                           17-Feb-2025 10:16               11647
svml_s_sincosf16_core-avx2.S                       17-Feb-2025 10:16                 928
svml_s_sincosf16_core.c                            17-Feb-2025 10:16                1168
svml_s_sincosf16_core_avx512.S                     17-Feb-2025 10:16               24114
svml_s_sincosf4_core-sse2.S                        17-Feb-2025 10:16                 917
svml_s_sincosf4_core.c                             17-Feb-2025 10:16                1163
svml_s_sincosf4_core_sse4.S                        17-Feb-2025 10:16               10991
svml_s_sincosf8_core-sse.S                         17-Feb-2025 10:16                 924
svml_s_sincosf8_core.c                             17-Feb-2025 10:16                1161
svml_s_sincosf8_core_avx2.S                        17-Feb-2025 10:16               12648
svml_s_sinf16_core-avx2.S                          17-Feb-2025 10:16                 912
svml_s_sinf16_core.c                               17-Feb-2025 10:16                1145
svml_s_sinf16_core_avx512.S                        17-Feb-2025 10:16               14362
svml_s_sinf4_core-sse2.S                           17-Feb-2025 10:16                 901
svml_s_sinf4_core.c                                17-Feb-2025 10:16                1140
svml_s_sinf4_core_sse4.S                           17-Feb-2025 10:16                6891
svml_s_sinf8_core-sse.S                            17-Feb-2025 10:16                 928
svml_s_sinf8_core.c                                17-Feb-2025 10:16                1138
svml_s_sinf8_core_avx2.S                           17-Feb-2025 10:16                6571
svml_s_sinhf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_sinhf16_core.c                              17-Feb-2025 10:16                1154
svml_s_sinhf16_core_avx512.S                       17-Feb-2025 10:16               13019
svml_s_sinhf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_sinhf4_core.c                               17-Feb-2025 10:16                1145
svml_s_sinhf4_core_sse4.S                          17-Feb-2025 10:16                9408
svml_s_sinhf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_sinhf8_core.c                               17-Feb-2025 10:16                1143
svml_s_sinhf8_core_avx2.S                          17-Feb-2025 10:16               11326
svml_s_tanf16_core-avx2.S                          17-Feb-2025 10:16                 912
svml_s_tanf16_core.c                               17-Feb-2025 10:16                1149
svml_s_tanf16_core_avx512.S                        17-Feb-2025 10:16               43527
svml_s_tanf4_core-sse2.S                           17-Feb-2025 10:16                 921
svml_s_tanf4_core.c                                17-Feb-2025 10:16                1140
svml_s_tanf4_core_sse4.S                           17-Feb-2025 10:16              108641
svml_s_tanf8_core-sse.S                            17-Feb-2025 10:16                 928
svml_s_tanf8_core.c                                17-Feb-2025 10:16                1138
svml_s_tanf8_core_avx2.S                           17-Feb-2025 10:16              113438
svml_s_tanhf16_core-avx2.S                         17-Feb-2025 10:16                 916
svml_s_tanhf16_core.c                              17-Feb-2025 10:16                1154
svml_s_tanhf16_core_avx512.S                       17-Feb-2025 10:16               17913
svml_s_tanhf4_core-sse2.S                          17-Feb-2025 10:16                 925
svml_s_tanhf4_core.c                               17-Feb-2025 10:16                1145
svml_s_tanhf4_core_sse4.S                          17-Feb-2025 10:16               49929
svml_s_tanhf8_core-sse.S                           17-Feb-2025 10:16                 932
svml_s_tanhf8_core.c                               17-Feb-2025 10:16                1143
svml_s_tanhf8_core_avx2.S                          17-Feb-2025 10:16               52047
w_exp.c                                            17-Feb-2025 10:16                  35
w_log.c                                            17-Feb-2025 10:16                  35
w_pow.c                                            17-Feb-2025 10:16                  35